The present invention relates to bus communication pathways and, in particular, to a time-multiplexed multi-speed bus that supports both low-speed bus operations and high-speed bus operations.
A bus is a communication pathway that connects two or more devices within a computer system. A bus is a shared transmission medium to which multiple devices can be connected. A signal transmitted by one device may be received by any other device attached to the bus, or even by multiple devices attached to the bus. A bus may contain from 8 to greater than 100 separate signal lines. At any given instant of time, each signal line is assigned to a particular meaning or function. The signal lines can be broadly classified into the following three groups: data lines, address lines, and control lines, although some signal lines time multiplex various combinations of these groups.
The data lines are used to move data from one device to another over the bus. Each data line corresponds to one bit of data. Generally, a bus contains some multiple of 8 data lines with each data line representing one bit of an 8-bit byte. The number of data lines contained in a bus is referred to as the width of the bus. Modern buses may contain 32, 64, 128, or a greater number of data lines. In addition, one or more error detecting or error correcting bits may be transferred on respective signal lines of a bus.
Address lines are used to identify the source or destination of a subsequent data transfer operation. Each device connected to a bus generally has a unique address that can be transmitted through the address lines to notify the device that it is the intended recipient of a following data transfer. As with the data lines, a bus generally contains some multiple of 8 address lines, although an error detecting bit, such as a parity bit, may be included. Common computer architectures use 16, 32, or 64-bit addresses.
Control lines are used by devices to specify operations like, for example, reading data and writing data, as well as for synchronizing access to the bus and for receiving notification of the reception and transmission of data. Certain control lines are shared by multiple devices, while other control lines are dedicated to specific devices.
One special control line is the clock signal line. Bus operations occur over one or more bus cycles. Each bus cycle is composed of one or more clock cycles. In normal operation, the clock signal line rapidly and regularly oscillates between a high state and a low state. One complete oscillation of the clock signal line represents one clock cycle. In a low-speed bus, the clock signal line oscillates with a relatively low frequency, like, for example, 33 megahertz. In a high-speed bus, the clock signal line oscillates with a relatively high frequency of 66 megahertz or 133 megahertz. However, the frequency of the clock signal may be reduced to reduce power consumption, particularly in battery powered portable computers.
A high-speed bus can complete a greater number of bus cycles in a given amount of time, and can thus execute a greater number of bus operations in a given amount of time, than a low-speed bus. A greater number of bus operations per unit of time corresponds to a greater data transfer rate, or bandwidth.
Modem computer systems, such as personal computers (xe2x80x9cPCsxe2x80x9d), employ a number of different buses that are often hierarchically organized. Using multiple buses, a computer architect is able to isolate certain high volume or time critical data exchanges between particular devices from lower volume or less critical data exchanges, respectively. FIG. 1 is a block diagram of a commonly-employed bus architecture within a currently-available PC 100. The various buses within the PC provide communication pathways between a central processing unit (xe2x80x9cCPUxe2x80x9d) 102, one or more main memories 104, several low-speed devices 106, such as storage or networking devices, a high-speed device 108, such as a gigabit local area network controller or a high-speed graphics device controller, and low-speed devices (not shown), such as a keyboard, mouse, printer or serial port, through a peripheral I/O port 113, such as an Ultra Port manufactured by National Semiconductor, connected to another low-speed bus 110 through a bus bridge 112. A system controller 114 serves within the PC 100 as a sort of terminal and transfer station for a number of important buses. The CPU 102 is connected to the system controller 114 via a CPU bus 116. Main memory 104 is connected to the system controller 114 via a memory bus 118. One or more low-speed devices 106 and the bus bridge 112 are generally connected to the system controller 114 via a 33 megahertz peripheral component interconnect (xe2x80x9cPCIxe2x80x9d) bus 120. High speed devices 108 are commonly connected to the system controller via a 66 megahertz PCI bus or a 133 megahertz advanced graphics processor (xe2x80x9cAGPxe2x80x9d) bus 121. The AGP bus is both a functional and physical superset of the PCI bus.
Buses are connected to the system controller 114 through a collection of pin connectors and logic circuits that together compose a bus interface. The system controller 114 shown in FIG. 1 contains, for example, a CPU bus interface 122, a memory bus interface 124, a low-speed PCI bus interface 126, and a high-speed PCI bus or AGP bus interface 128. The connection interfaces of the system controller 114 and of other integrated circuit devices (not shown) comprise a large number of terminals, including the terminals of the bus interfaces. These terminals are most commonly pin connectors positioned along the sides of packaging for the integrated circuit, but they may also have other forms, such as terminal pads adapted to be mounted on a printed circuit board using a ball grid array. The density of terminals, such as connector pins positioned along the edges of such devices, is a critical limiting factor in the design of modern computer systems. A device that supports an increased functional interface generally requires an increased number of terminals. Increasing the number of terminals, however, adds to the expense and detracts from the reliability of a device, and there are practical limits to the number of terminals that can be incorporated into a given device. While a larger number of terminals can be accommodated by making the package for the integrated circuit larger, doing so requires signals coupled to and from the integrated circuit over a longer signal path. Increasing the length of the signal paths may create internal timing problems and it limits the operating speed of the integrated circuit.
As the width of buses has increased from 16 to 32, and now, commonly, to 64, the number of terminals that comprise a bus interface has also correspondingly increased. In order to minimize the number of terminals required for a bus interface, bus architects have developed a strategy known as time multiplexing. Using this strategy, bus architects are able to use the same physical signal lines both for data transfer and for addressing. In other words, the data lines and the address lines are physically coexistent. Certain of the control lines on the bus can be asserted within a bus cycle to select either an addressing mode or a data transfer mode for bus operation. At any particular instant of time, the data/address signal lines are used either for data transfer or for addressing. At the cost of the addition of several control lines for controlling the selection of either a data transfer mode or an addressing mode, 16, 32, or 64 signal lines that would otherwise be dedicated solely for addressing or for data transfer can be eliminated. Time multiplexing thus provides a way to decrease the number of physical signal lines required to implement a bus and to correspondingly decrease the number of terminals required for the bus interface.
In FIG. 1, the low-speed bus 120 and the high-speed bus 121 are shown to be comprised of both broad sets of signal lines 130 and 132 and narrow sets of signal lines 134 and 136. The broad sets of signal lines 130 and 132 include the shared data/address lines and a majority of the control lines. The narrow sets of signal lines 134 and 136 include a small number of control lines related to control of the bus cycles.
Although use of time multiplexing has enabled computer architects to control the number of terminals required for a particular bus interface, increasing demands for bandwidth and connectivity within computer systems has resulted in the use of an increasing number of different buses. Modern high-speed graphics devices, for example, require rapid transmission of a very high volume of data and therefore require high-speed buses such as the 66 megahertz PCI bus or the 133 megahertz AGP bus. Thus, as shown in FIG. 1, a low-speed bus 120 and a high-speed bus 121 are both needed to provide the bandwidth requirements for the increasing number of low-speed peripheral devices and the high-speed graphics devices commonly required in a modem PC. Many of the low-speed devices cannot be connected to a high-speed bus such as a 66 megahertz PCI bus or a 133 megahertz AGP bus, because the high-speed bus cannot tolerate large capacitive loads. Each additional bus interface requires additional pin connectors that increase the expense and decrease the reliability of the devices that contain them. The Intel 440LX bus bridge, for example, currently requires 492 pin connectors to support 4 buses, including a 32-bit PCI bus and a 32-bit AGP bus. An increase of the width of the PCI and AGP buses to 64 bits will correspondingly increase the number of pin connectors required in the Intel 440LX bus bridge and similar devices. A need has therefore been recognized for a device that incorporates both low-speed and high-speed bus interfaces while, at the same time, minimizes the number of pin connectors that need to be added to the device.
One embodiment of the present invention in a computer provides a multiplexed multi-speed bus that supports low-speed bus operations and high-speed bus operations over shared time-multiplexed control, data and address signal lines. In this embodiment, both low-speed peripheral devices and high-speed peripheral devices are connected to a single set of data and address signal lines. The low-speed peripheral devices are separately connected, in addition, to a small set of dedicated low-speed control lines. Similarly, the high-speed peripheral devices are separately connected to a small set of dedicated high-speed control lines. Bus cycles are controlled during high-speed operation of the bus by the high-speed control lines, and are controlled during low-speed operation of the bus by the low-speed control lines. When a bus operation is initiated by or directed to a low-speed peripheral device, the bus is operated at low speed. When a bus operation is initiated by or directed to a high-speed peripheral device, the bus is operated at high speed. Bus operations involving both a low-speed and a high-speed peripheral device are initially at the speed of the peripheral device transmitting data to a storage buffer (not shown) in the system controller 114. The system controller 114 then transmits the data from the storage buffer to the peripheral device receiving the data at the speed of the receiving peripheral device. Thus, in this embodiment of the present invention, two different levels of time multiplexing are employed. At one level of time multiplexing, both data and addresses are transmitted over a common set of signal lines. At a second level of time multiplexing, both low-speed and high-speed bus operations are conducted over the shared data and address signal lines. This embodiment of the present invention essentially combines two different physical buses into a single physical bus and two corresponding bus interfaces into a single bus interface that requires far less terminals than the sum of the terminals required for the two separate bus interfaces.